Test Point Insertion For Low Test Pattern Counts

ABSTRACT

Various aspects of the disclosed technology relate to conflict-reducing test point insertion techniques. Locations in a circuit design for inserting test points are determined based on internal signal conflicts caused by detecting multiple faults with a single test pattern. Test points are then inserted at the locations. The internal signal conflicts may comprise horizontal conflicts, vertical conflicts, or both. The test points may comprise control points, observation points, or both.

RELATED APPLICATIONS

This application claims the benefit of U.S. Provisional PatentApplication No. 62/064,900, filed on Oct. 16, 2014, and naming JanuszRajski et al. as inventors, which application is incorporated entirelyherein by reference.

FIELD OF THE DISCLOSED TECHNIQUES

The presently disclosed techniques relates to the field of circuittesting technology. Various implementations of the disclosed techniquesmay be particularly useful for reducing test data by inserting testpoints.

BACKGROUND OF THE DISCLOSED TECHNIQUES

Contemporary electronic design automation (EDA) tools in general andautomatic test pattern generation (ATPG) in particular are capable ofproducing tests that offer high coverage of failures occurring in largeand complex semiconductor digital designs. Notwithstanding the successof test compression, ATPG-produced test sets continue to grow atalarming rates. This is mainly caused by: 1) designs feature a largenumber of clock domains with staggeringly complex clocking schemes; 2) atypical test generation process for at-speed patterns includes a largenumber of steps, with all of them handling several clock sequences; 3)the ratios of gates and flip-flops are large and still increasing, butthe number of I/O pins does not follow the continuing growth in thenumber of gates and flip-flops inside a chip; 4) tested circuitscomprise logic of large combinational depths; 5) automatically generatedregister-transfer level (RTL) designs feature complex control logiccircuits; and 6) a typical test set contains many long tail testpatterns—although these patterns contain very few specified bits, theirmutual conflicts effectively prevent compression-aware merging of testcubes.

Moreover, the gate level abstraction and traditional fault models(stuck-at, transition) are no longer sufficient to ensure high qualityand low-DPM (defects per million) metrics for state-of-the-art digitalcircuits. As a result, the next generation tools are expected to targetnovel timing-related and actual-layout-related fault models andpatterns, such as n-detect, embedded-multi-detect, or recently proposedcell-aware. Unfortunately, this trend leads to inflated test sets thatrequire more storage than many external testers can provide. The testapplication time is an even more evident efficiency limiting andcost-increasing factor, which has become an unprecedented challenge inthe testing of embedded systems, automotive electronics, orsystem-on-chip designs, to name just a few.

The disclosed technology relates to inserting conflict-reducing testpoints which can reduce test pattern counts. Traditionally, test pointinsertion techniques attempt to improve the fault detection likelihoodwhile minimizing a necessary hardware real estate. They select internallines in a circuit to subsequently add control points or observationpoints in order to activate (excite) faults or observe them,respectively. Identification of potential test point candidates is acomplex problem because of several interacting factors. In general,optimal test point insertion for circuits with reconvergent fan-outs isan NP-complete problem and, hence, numerous empirical guidelines andapproximate techniques have been proposed to identify suitable testpoints (control points and observation points) locations and improve theoverall circuit testability.

Depending on how a test point is driven or observed, its insertion mayrequire a few extra gates and wires routed to or from additionalflip-flops to be included in scan chains. As it introduces area andperformance penalty, the number of test points is usually limited.Furthermore, the identification of test points must be computationallyinexpensive despite the structural complexity of large designs.

The first systematic TPI method was introduced in Briers, A. J. andTotton, K. A. E., “Random Pattern Testability By Fault Simulation”,Proceedings of the IEEE International Test Conference, ITC'86. 274-281,1986, which is incorporated herein by reference. Simulations are usedfirst to obtain profiles of fault propagation and correlations betweeninternal signals. Test points are then inserted to break signalcorrelations.

Similarly, the technology disclosed in Iyengar, V. S. and Brand, D.,“Synthesis Of Pseudorandom Pattern Testable Designs”, Proceedings of theIEEE International Test Conference, ITC'89. 501-508, 1989, which isincorporated herein by reference, employs fault simulation to identifygates that block fault propagation and inserts test points to regainsuccessful propagation of fault effects.

A divide-and-conquer approach disclosed in Tamarapalli, N. and Rajski,J., “Constructive Multiphase Test Point Insertion For Scan-Based BIST”,Proceedings of the IEEE International Test Conference, ITC'96. 649-658,1996, which is incorporated herein by reference, partitions the entiretest into multiple phases. Within each phase, a group of test points isactivated to maximize the fault coverage calculated over the set ofstill-undetected faults. A probabilistic fault simulation, whichcomputes the impact of a new control point in the presence of thecontrol points already selected, is used as a vehicle to select testpoints.

To avoid time-consuming simulations, other methods utilize thecontrollability and observability measures to identify thehard-to-control and hard-to-observe sectors of a circuit, at which testpoints are subsequently inserted. In particular, the schemes disclosedin Cheng, K.-T., and Lin, C.-J., “Timing-Driven Test Point Insertion ForFull-Scan And Partial-Scan BIST”, Proceedings of the IEEE InternationalTest Conference, ITC'95, 506-514, 1995 and Nakao, M., Hatayama, K., andHighasi, I., “Accelerated test points selection method for scan-basedBIST”, Proceedings of the IEEE Asian Test Symposium, ATS'97, 359-364,1997, which are incorporated herein by reference, use COP(Controllability Observability Program) estimates to extract testabilitydata. Hybrid testability measures based on the SCOAP (SandiaControllability/Observability Analysis Program) metrics, cost functions,a gradient-based method, or signal correlation are used as well todetermine the best TP sites.

These conventional test point insertion techniques can improve the faultdetection likelihood, but may not affect test pattern counts at all. Asreported in Kumar, A., Rajski, J., Reddy, S. M., and Rinderknecht, T.,“On the generation of compact deterministic test sets for BIST readydesigns”, Proceedings of the IEEE Asian Test Symposium, ATS'13, 201-206,2013, which is incorporated herein by reference, the reduction of thesecounts can average anywhere between 0 and 35%. Therefore, it isdesirable to develop new test point insertion techniques that can reducethe volume of test data.

BRIEF SUMMARY OF THE DISCLOSED TECHNIQUES

Various aspects of the disclosed technology relate to conflict-reducingtest point insertion techniques. In one aspect, there is a method,executed by at least one processor of a computer, comprising:determining locations in a circuit design for inserting test pointsbased on internal signal conflicts caused by detecting multiple faultswith a single test pattern; inserting test points at the locations.

In another aspect, there is a method, executed by at least one processorof a computer, comprising: computing internal signal conflict metrics;adding/adjusting test points to/at locations selected based on internalsignal conflict metrics; and repeating the computing and theadding/adjusting until one of one or more predetermined conditions ismet.

In still another aspect, there are one or more non-transitorycomputer-readable media storing computer-executable instructions forcausing one or more processors to perform a method, wherein the methodcomprises: determining locations in a circuit design for inserting testpoints based on internal signal conflicts caused by detecting multiplefaults with a single test pattern; inserting test points at thelocations.

In still another aspect, there are one or more non-transitorycomputer-readable media storing computer-executable instructions forcausing one or more processors to perform a method, wherein the methodcomprises: adding/adjusting test points to/at locations selected basedon internal signal conflict metrics; and repeating the computing and theadding/adjusting until one of one or more predetermined conditions ismet.

In the above aspects, the test points may be control points. Theinternal signal conflicts may comprise horizontal conflicts. Thehorizontal conflict of a branch of a net in the circuit design may bemeasured based on numbers of faults being blocked by setting the branchto a signal of “0” and of “1”, respectively. Additionally oralternatively, the internal signal conflicts may comprise verticalconflicts. The vertical conflict of a stem of a net may be measuredbased on numbers of conflicts due to fault propagation conditions andlogic values being forward-implied by the conditions.

Certain inventive aspects are set out in the accompanying independentand dependent claims. Features from the dependent claims may be combinedwith features of the independent claims and with features of otherdependent claims as appropriate and not merely as explicitly set out inthe claims.

Certain objects and advantages of various inventive aspects have beendescribed herein above. Of course, it is to be understood that notnecessarily all such objects or advantages may be achieved in accordancewith any particular embodiment of the disclose techniques. Thus, forexample, those skilled in the art will recognize that the disclosetechniques may be embodied or carried out in a manner that achieves oroptimizes one advantage or group of advantages as taught herein withoutnecessarily achieving other objects or advantages as may be taught orsuggested herein.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a programmable computer system with which variousembodiments of the disclosed technology may be employed.

FIG. 2 illustrates an example of a test point insertion tool accordingto various embodiments of the disclosed technology.

FIG. 3 illustrates a flowchart 300 showing a process of test pointinsertion that may be implemented according to various examples of thedisclosed technology.

FIG. 4 illustrates an example of internal signal conflicts.

FIG. 5 illustrates an example of a circuit for explaining fault blockingmechanisms.

FIG. 6 illustrates another example of a circuit for explaining faultblocking mechanisms.

FIG. 7 illustrates an example of horizontal conflicts.

FIG. 8 illustrates another flowchart showing a process of test pointinsertion that may be implemented according to various examples of thedisclosed technology.

FIG. 9 illustrates an example of vertical conflicts.

DETAILED DESCRIPTION OF THE DISCLOSED TECHNIQUES

General Considerations

Various aspects of the disclosed technology relate to conflict-reducingtest point insertion techniques. In the following description, numerousdetails are set forth for the purpose of explanation. However, one ofordinary skill in the art will realize that the disclosed technology maybe practiced without the use of these specific details. In otherinstances, well-known features have not been described in details toavoid obscuring the disclosed technology.

Some of the techniques described herein can be implemented in softwareinstructions stored on a computer-readable medium, software instructionsexecuted on a computer, or some combination of both. Some of thedisclosed techniques, for example, can be implemented as part of anelectronic design automation (EDA) tool. Such methods can be executed ona single computer or on networked computers.

Although the operations of the disclosed methods are described in aparticular sequential order for convenient presentation, it should beunderstood that this manner of description encompasses rearrangements,unless a particular ordering is required by specific language set forthbelow. For example, operations described sequentially may in some casesbe rearranged or performed concurrently. Moreover, for the sake ofsimplicity, the disclosed flow charts and block diagrams typically donot show the various ways in which particular methods can be used inconjunction with other methods. Additionally, the detailed descriptionsometimes uses terms like “determine” and “insert” to describe thedisclosed methods. Such terms are high-level abstractions of the actualoperations that are performed. The actual operations that correspond tothese terms will vary depending on the particular implementation and arereadily discernible by one of ordinary skill in the art.

Also, as used herein, the term “design” is intended to encompass datadescribing an entire integrated circuit device. This term also isintended to encompass a smaller group of data describing one or morecomponents of an entire device, however, such as a portion of anintegrated circuit device. Still further, the term “design” also isintended to encompass data describing more than one microdevice, such asdata to be used to form multiple microdevices on a single wafer.

Illustrative Operating Environment

Various examples of the disclosed technology may be implemented throughthe execution of software instructions by a computing device, such as aprogrammable computer. Accordingly, FIG. 1 shows an illustrative exampleof a computing device 101. As seen in this figure, the computing device101 includes a computing unit 103 with a processing unit 105 and asystem memory 107. The processing unit 105 may be any type ofprogrammable electronic device for executing software instructions, butwill conventionally be a microprocessor. The system memory 107 mayinclude both a read-only memory (ROM) 109 and a random access memory(RAM) 111. As will be appreciated by those of ordinary skill in the art,both the read-only memory (ROM) 109 and the random access memory (RAM)111 may store software instructions for execution by the processing unit105.

The processing unit 105 and the system memory 107 are connected, eitherdirectly or indirectly, through a bus 113 or alternate communicationstructure, to one or more peripheral devices. For example, theprocessing unit 105 or the system memory 107 may be directly orindirectly connected to one or more additional memory storage devices,such as a “hard” magnetic disk drive 115, a removable magnetic diskdrive 117, an optical disk drive 119, or a flash memory card 121. Theprocessing unit 105 and the system memory 107 also may be directly orindirectly connected to one or more input devices 123 and one or moreoutput devices 125. The input devices 123 may include, for example, akeyboard, a pointing device (such as a mouse, touchpad, stylus,trackball, or joystick), a scanner, a camera, and a microphone. Theoutput devices 125 may include, for example, a monitor display, aprinter and speakers. With various examples of the computer 101, one ormore of the peripheral devices 115-125 may be internally housed with thecomputing unit 103. Alternately, one or more of the peripheral devices115-125 may be external to the housing for the computing unit 103 andconnected to the bus 113 through, for example, a Universal Serial Bus(USB) connection.

With some implementations, the computing unit 103 may be directly orindirectly connected to one or more network interfaces 127 forcommunicating with other devices making up a network. The networkinterface 127 translates data and control signals from the computingunit 103 into network messages according to one or more communicationprotocols, such as the transmission control protocol (TCP) and theInternet protocol (IP). Also, the interface 127 may employ any suitableconnection agent (or combination of agents) for connecting to a network,including, for example, a wireless transceiver, a modem, or an Ethernetconnection. Such network interfaces and protocols are well known in theart, and thus will not be discussed here in more detail.

It should be appreciated that the computer 101 is illustrated as anexample only, and it not intended to be limiting. Various embodiments ofthe disclosed technology may be implemented using one or more computingdevices that include the components of the computer 101 illustrated inFIG. 1, which include only a subset of the components illustrated inFIG. 1, or which include an alternate combination of components,including components that are not shown in FIG. 1. For example, variousembodiments of the disclosed technology may be implemented using amulti-processor computer, a plurality of single and/or multiprocessorcomputers arranged into a network, or some combination of both.

Test Point Insertion Tools And Methods

FIG. 2 illustrates an example of a test point insertion tool accordingto various embodiments of the disclosed technology. As seen in thefigure, the test point insertion tool 200 includes two units: aninsertion location determination unit 220 and a test point insertionunit 240. Some implementations of the diagnosis tool 200 may cooperatewith (or incorporate) one or both of an input database 205 and an outputdatabase 285.

As will be discussed in more detail below, the insertion locationdetermination unit 220 determines locations in a circuit design forinserting test points based on internal signal conflicts. The test pointinsertion unit 240 then inserts test points at the determined locations.

As previously noted, various examples of the disclosed technology may beimplemented by a computing system, such as the computing systemillustrated in FIG. 1. Accordingly, one or both of the insertionlocation determination unit 220 and the test point insertion unit 240may be implemented by executing programming instructions on one or moreprocessors in a computing system such as the computing systemillustrated in FIG. 1. Correspondingly, some other embodiments of thedisclosed technology may be implemented by software instructions, storedon a non-transitory computer-readable medium, for instructing one ormore programmable computers/computer systems to perform the functions ofone or both of the insertion location determination unit 220 and thetest point insertion unit 240. As used herein, the term “non-transitorycomputer-readable medium” refers to computer-readable medium that arecapable of storing data for future retrieval, and not propagatingelectro-magnetic waves. The non-transitory computer-readable medium maybe, for example, a magnetic storage device, an optical storage device, a“punched” surface type device, or a solid state storage device.

It also should be appreciated that, while the insertion locationdetermination unit 220 and the test point insertion unit 240 are shownas separate units in FIG. 2, a single computer (or a single processorwithin a master computer) may be used to implement both of these unitsat different times, or components of these units at different times.

With various examples of the disclosed technology, the input database205 and the output database 285 may be implemented using any suitablecomputer readable storage device. That is, either of the input database205 and the output database 285 may be implemented using any combinationof computer readable storage devices including, for example,microcircuit memory devices such as read-write memory (RAM), read-onlymemory (ROM), electronically erasable and programmable read-only memory(EEPROM) or flash memory microcircuit devices, CD-ROM disks, digitalvideo disks (DVD), or other optical storage devices. The computerreadable storage devices may also include magnetic cassettes, magnetictapes, magnetic disks or other magnetic storage devices, punched media,holographic storage devices, or any other non-transitory storage mediumthat can be used to store desired information. While the input database205 and the output database 285 are shown as separate units in FIG. 2, asingle data storage medium may be used to implement some or all of thesedatabases.

FIG. 3 illustrates a flowchart 300 showing a process of test pointinsertion that may be implemented according to various examples of thedisclosed technology. FIG. 8 illustrates another flowchart 800 showing aprocess of test point insertion that may be implemented according tovarious examples of the disclosed technology. For ease of understanding,methods of test point insertion that may be employed according tovarious embodiments of the disclosed technology will be described withreference to the test point insertion tool 200 illustrated in FIG. 2 andthe flow charts 300 and 800 in FIGS. 3 and 8, respectively. It should beappreciated, however, that alternate implementations of a test pointinsertion tool may be used to perform the methods of test pointinsertion in the flow chart 300/800 according to various embodiments ofthe disclosed technology. In addition, it should be appreciated thatimplementations of the test point insertion tool 200 may be employed toimplement methods of test point insertion according to differentembodiments of the disclosed technology other than the ones illustratedby the flow charts 300 and 800.

In operation 310 of the flow chart 300, the insertion locationdetermination unit 220 determines locations in a circuit design forinserting test points based on internal signal conflicts caused bydetecting multiple faults with a single test pattern. In operation 320,the test point insertion unit 240 inserts test points at the determinedlocations.

An internal signal conflict arises out of incompatible decisions made oninternal lines due to fault excitation, backward justifications, orfault propagation of multiple faults. Due to the internal signalconflict, these faults cannot be detected by the same test pattern.

FIG. 4 illustrates an example of an internal signal conflict. Topropagate faults from the cone of logic 410 through an AND gate 420,input s₁ (460) of the AND gate 420 must be set to 1. On the other hand,to propagate faults populating cone 430, input s₂ (470) of an OR gate440 must assume the value of 0. Clearly, a conflict occurs at stem s₀(450) because of mutually opposed fault propagation requirements thatcorrespond to different non-controlling values for gates driven by acommon stem. As a result, these particular faults (referred to as faultsC₁ (410) and C₂ (430)) cannot be detected by the same test pattern.

It is worth noting that simultaneous detection of faults C₁ and C₂ wouldbe possible provided a control point is placed on one of the stembranches. For example, one can insert a 1-injection circuit such as anOR gate on branch s₁ (460), allowing 1-controllability of this line (anOR control point). Alternatively, a 0-injection circuit such as an ANDgate can be placed on branch s₂ (470), allowing 0-controllability ofthis particular net (an AND control point).

The internal signal conflicts may manifest themselves in a variety ofways. In some embodiments of the disclosed technology, the internalsignal conflicts comprise horizontal conflicts. Before defining thehorizontal conflicts, several related concepts employed to assess afault-blocking mechanism will be explained first.

The number of faults whose propagation is blocked (for brevity—blockedfaults) is determined based on the results of forward value propagation.Having set a given internal line to a logic value v, this valuepropagates subsequently forward as long as the outputs of gates visitedalong propagation paths can be uniquely determined. In particular, itapplies to scenarios where v remains a controlling value for a visitedgate G, or all inputs of G assume a non-controlling value. In FIG. 5,for example, if one sets stem s₀ (505) to 1, then it causes the outputof gates 530, 550 and 560 to assume the value of 0. On the other hand,assigning the value of 0 to s₀ sets the output of gates 510 and 540 to0, as it is a controlling value for the AND gates. Since gates 510 and540 drive cone C5, further signal propagation depends on its internalstructure.

Every AND, NAND, OR, and NOR gate is said to block faults if thecontrolling value reaches its input(s). For instance, faults C2 and C4are blocked due to 1 at input s₂ (535). Also, faults affecting input 525of gate 560 will be blocked, as their only propagation path leads to theoutput of gate 560. Finally, 0 at input s₁ (535) of gate 510 blocks itssecond input 527 and, thus, any fault observed on the output of C1cannot move further towards a circuit output. The same applies to faultspropagating through C3.

Additional rules may apply to fault propagation through fan-out-freeregions, i.e., treelike gate structures. For simplicity's sake, it isassumed that cones presented in figures herein are fan-out-free regions.When a fan-out-free region has a single output and is consideredblocked, then all faults within that fan-out-free region are unable topropagate to the output (e.g., faults C₁ and C₃ in FIG. 5). However, asan FFR may feature an output fan-out, fault propagation conditionsdepend on a combined status of all of its output branches.

Consider a circuit shown in FIG. 6. Let output s₀ (610) of C₂ be set to0. It results in blocking all fan-out branches of C₁ and, therefore,faults C₁ cannot propagate to the outputs of the two AND gates 620 and630. On the other hand, if the same C₁ featured additional outputbranches that do not reach gates 620 and 630 or fan-out-free regionsalready blocked, then its internal faults would not be blocked due tothe existence of alternative propagation routes.

The main concept of a horizontal conflict is illustrated in FIG. 4. Alogic value of 1 is necessary to propagate faults through the AND gate420, whereas a logic value of 0 is needed to achieve the same with theOR gate 440. Hence, if stem s₀ (450) is set to 0, then faults C₁ (410)are blocked. Similarly, applying 1 to stem s₀ (450) blocks faults C₂(420). The degree of a horizontal conflict at a given stem s may bemeasured by using the following metric:

H_(s)=min {u_(s), U_(s)}  (1)

where u_(s) and U_(s) are quantities of faults blocked by setting stem sto 0 and 1, respectively. As can be seen, the degree of horizontalconflicts is measured as a minimal number of blocked faults. It relatesto a lower bound of conflicts at a given stem or, stated differently, itindicates the amount of faults whose blocking is inevitable.

In the example illustrated in FIG. 4, assume C₁ (410) and C₂ (420) hostD_(C1)=4,000 faults and D₂=7,000 faults, respectively. The number ofblocked faults at the stem is equal to the sum of blocked faultsrecorded on all fan-out branches. In this case, setting the stem s₀(450) to 0 blocks propagation of faults C₁ (410), i.e., u_(s)=D_(C1).Similarly, setting the stem C₁ (410) to 1 blocks propagation of faultsC₂ (420), i.e., U_(s)=D_(C2). Finally, H_(s)=min {u_(s), U_(s)}=min{D_(C1), D_(C2)}=D_(C1)=4,000, according to Eq. 1. To propagate faultsC₁ (410) and C₂ (420) at the same time, a control point may be deployedat either of the two branches, s₁ (460) and s₂ (470), as discussedpreviously.

FIG. 7 illustrates a slightly more complicated case of horizontalconflicts. In the figure, a stem 710 features three output branches 720,730 and 740. Cones C₁ (750), C₂ (760), and C₃ (770) drive thecorresponding gates 755. 765 and 775, respectively. Assume thatD_(C1)=1,000, D_(C2)=8,000, and D_(C3)=5,000, representing the number offaults hosted by the cones C₁ (750), C₂ (760), and C₃ (770),respectively. Then, for the stem 710, u_(s)=D_(C2)=8,000 andU_(s)=D_(C1)+D_(C3)=6,000. Thus, H_(s)=U_(s)=6,000. To reduce theconflict, control points may be inserted on some branches. For example,an OR gate may be inserted on the branch 730 and an AND gate may beinserted on the branch 740. As such, u_(s)=0 and U_(s)=1,000.

The number of test points is usually limited as the test point insertionintroduces area and performance penalty. One solution is to use athreshold denoted as β for blocked faults. Only branches that have thenumber of blocked faults above the threshold β are considered for thetest point insertion. The threshold β may be user-defined andcircuit-specific.

The flow chart 800 is used here to illustrate how test points areinserted to reduce horizontal conflicts according to some embodiments ofthe disclosed technology. In operation 810, the insertion locationdetermination unit 220 computes internal signal conflict metrics such asthose for horizontal conflict metrics. In operation 820, the test pointinsertion unit 240 adds/adjusts test points on locations selected basedon the internal signal conflict metrics. For example, appropriate testpoints are added to branches having the number of blocked faults aboveβ. Or branches having the first n (n>0) largest blocked faults. If noneof one or more predetermined termination conditions is met, internalsignal conflict metrics are recomputed on the design with the added testpoints and the process repeats. When the operation 820 is repeated, someof the existing test points may be replaced with new test points.

Another threshold for H_(s) (denoted as γ) may be introduced to reducethe computation time. Only branches on a stem with H_(s)>γ may beconsidered for the test point insertion. When the operation 810 isrepeated, H_(s) is also recomputed. One example of a predeterminedtermination condition is all eligible branches are examined.

It is worth noting that an overall profile of internal signal conflictskeeps changing during test point insertion process. Thus, test pointsalready in may visibly impact further test point insertion decisions.

Conflicts between logic values when running ATPG may also occur in avertical manner. Four parameters may be employed as the verticalconflict metrics: b_(x) and B_(x)—the number of 0s and 1s, respectively,required on net x to propagate faults through all relevant gates, andf_(x) and F_(x)—the number of forward-implied values of 0 and 1,respectively, on net x due to earlier backward justifications.

FIG. 9 illustrates an example of vertical conflicts. If a gate 2 is setto 0 to enable propagation of faults C₃ (930), then at least one of itsinputs 922 and 927 needs to be set to 0. This precludes propagation offaults C₁ (910), faults C₂ (920), or both. Propagation of faults C₄(940) is also not possible. On the other hand, having 1 on the output(925) of the gate 2 (as a result of attempts to propagate faults C₁(910) and faults C₂ (920)) blocks faults C₃ (930). As can be seen, a“vertical” conflict occurs at the stem between logic values beingforward-implied and those resulting from backward justifications thatare needed to propagate different groups of faults.

To enable propagation of faults C₃ (930), an input x₁ (947) of the gate4 has to be set to 0 at least D_(C3) times, i.e., b_(x1)=D_(C3). As 1 isthe controlling value for the OR gate 4, B_(x1)=0 (this value wouldblock any fault propagation). Assume that b_(y)=0 and B_(y)=0 for theother input y (942) of the gate 4. This is because faults that maypropagate to input x₁ (947) of gate (4) may also propagate to input x₂of the gate 5, and thus there are no necessary assignments associatedwith y (942). However, if the gate 4 featured another input coupled to afan-out-free region (say C₅), then b_(y) and B_(y) would assume nonzerovalues as the gate 4 would be a part of the only propagation path forfaults originating in C₃.

To determine b_(x0) and B_(x0) for a fan-out stem x₀ having fan-outbranches x₁, x₂, . . . x_(n), the following formulas may be used:

b _(x0) =b _(x0) +b _(x2) + . . . +b _(xn)   (2)

B _(xo) =B _(x1) +B _(x2) + . . . . +B _(xn)   (3)

The value of b_(x) (B_(x)) for line x equals the number of blockedfaults when x is set to 1 (0). By using this contrapositive rule, onecan easily implement a circuit-tracing-based technique to arrive withestimation of b_(x) and B_(x). The fan-out stem x₀ (925) in the exampleshown in FIG. 9 has two branches x₁ (947) and x₂ (949). Accordingly,b_(x0)=b_(x1)+b_(x2)=U_(x0)=D_(C3)+0=D_(C3) andB_(x0)=B_(x1)+B_(x2)=u_(x0)=0+D_(C4)=D_(C4) (see FIG. 9)

The vertical conflict analysis may also involve information regardingthe numbers f_(x) and F_(x) of 0s and 1s occurring at a given line x asa result of the justification of other gates. For a fan-out branchx_(k), the number f_(xk) of 0s is a sum of f_(x0) (the number of 0simplied on stem x₀) and the number of 0s required by the remainingbranches of the same stem in order to propagate faults, i.e.,

f _(xk) =f _(x0)+Σb_(xi) i≠k   (4)

Similarly, one can determine F_(xk). As an example, consider computationof and F_(x1) for the gate 4 in FIG. 9. The number of 0s reaching itsinput x₁ (947), f_(x1), is equal to the number of forward implied 0s onstem x₀ (925), f_(x0), plus the number b_(x2) of 0s required at input x₂(949) of the gate 5 to propagate faults C4 (940). As can be seen in thefigure, b_(x2)=0 since 0 is a controlling value for an AND gate. As aresult, f_(x1)=f_(x0). On the other hand, the number of 1s (F_(x1))equals the number of 1s at x₀ (925), F_(x0), plus 1s needed to propagatefaults C4 (940), B_(x2). Thus, F_(x1)=F_(x0)+B_(x2).

In addition to fan-out branches, values off and F for outputs ofdifferent types of gates need to be determined. Consider the gate 2 inFIG. 9. Let inputs v₀ (922) and w₀ (927) be primary ones. Inputs v₁(912) and w₂ (917) (and hence v₂ (922) and w₁ (927)) have to be set to 1in order to propagate faults C1 (910) and C2 (920) at least D_(C1) andD_(C2) times, respectively. However, to determine the total number of 0sand 1s seen at the inputs of gate (2), one should take into account 0sand 1s implied forward through stems v₀ and w₀. Since they are primaryinputs, f_(v0), F_(v0), f_(w0), and F_(w0) are all equal to 0. ThusF_(v2)=D_(C1) and F_(w1)=D_(C2). Moreover, f_(v2) and f_(w1) are both 0,as 0 is a controlling value for the gates 1 and 3. The number F_(x0) offorward implied 1s through the gate 2 is a function of F_(v2) andF_(w1). The value of F_(x0) may be defined as the minimum of the numbersof 1s at the inputs of the gate 2. On the other hand, as 0 is acontrolling value for the AND gate, the number f_(x0) of 0s propagatedthrough the gate 2 can be expressed as the maximum of the numbers of 0sat its inputs (f_(v2) and f_(w1)). In this particular case, a value off_(x0) is 0 because neither the gate 1 nor the gate 3 requires 0 topropagate faults C1 or C2.

The values of f_(x0) and F_(x0) are obtained by structural analysis of acircuit net list in conjunction with its fault list to find faults thatwould otherwise be blocked, if 1 and 0 are applied, respectively, to agate input. Given the numbers f_(k) and F_(k) of required 0s and 1s on agate k-th input, the corresponding output metrics f_(s) and F_(s) may becomputed by using the following formulas:

f_(s)=f_(k) f_(s)=F_(k)   (5a)

F_(s)=F_(k) F_(s)=f_(k)   (5b)

f_(s)=max{f_(k)} f_(s)=min{F_(k)}  (6a)

F_(s)=min{F_(k)} F_(s)=max{f_(k)}  (6b)

F_(s)=min{f_(k)} f_(s)=max{F_(k)}  (7a)

F_(s)=max{F_(k)} F_(s)=min{f_(k)}  (7b)

f _(s)=(min{f _(a) ,f _(b)}+min{F _(a) ,F _(b)})/2

F _(s)=(min{f _(a) ,F _(b)}+min{F _(a) ,f _(b)})/2   (8)

The above equations correspond to logic gates as follows: buffer (5a),inverter (5b), AND (6a), NAND (6b), OR (7a), NOR (7b), and 2-input XOR(8). One can arrive with formulas for other (complex) gates in a similarmanner.

Having defined the basic metrics, a measure of a vertical conflict atstem s may be derived. In this particular case, one can be interested inestimation of a lower bound of conflicts between values b_(s), F_(s) andf_(s), B_(s). The degree of a vertical conflict at a given stem s may bemeasured by using the following equation:

V_(s)=max{min{b_(s),F_(s)}, min{B_(s),f_(s)} }  (9)

As can be seen, Eq. 9 estimates the amount of inconsistency betweensignals required due to fault propagation conditions and logic valuesbeing forward implied by such decisions. Inserting a test point at astem can alleviate this type of conflicts. A type of control point isselected in such a way that if V_(s)=min{b_(s),F_(s)}, then an ANDcontrol point may be used. Otherwise, that is, V_(s)=min{B_(s),f_(s)},an OR control point may be inserted.

Similar to reducing horizontal conflicts discussed previously, theprocess shown by the flow chart 800 may be employed to insert testpoints for reducing vertical conflicts. Horizontal and verticalconflicts may be analyzed and processed at the same time or in sequence.

Conclusion

While the disclosed techniques has been described with respect tospecific examples including presently preferred modes of carrying outthe disclosed techniques, those skilled in the art will appreciate thatthere are numerous variations and permutations of the above describedsystems and techniques that fall within the spirit and scope of thedisclosed techniques as set forth in the appended claims. For example,while specific terminology has been employed above to refer toelectronic design automation processes, it should be appreciated thatvarious examples of the disclosed techniques may be implemented usingany desired combination of electronic design automation processes.

What is claimed is:
 1. A method, executed by at least one processor of acomputer, comprising: determining locations in a circuit design forinserting test points based on internal signal conflicts caused bydetecting multiple faults with a single test pattern; inserting testpoints at the locations.
 2. The method recited in claim 1, wherein thetest points are control points.
 3. The method recited in claim 1,wherein the internal signal conflicts comprise horizontal conflicts. 4.The method recited in claim 3, wherein the horizontal conflict of abranch of a net in the circuit design is measured based on numbers offaults being blocked by setting the branch to a signal of “0” and of“1”, respectively.
 5. The method recited in claim 1, wherein theinternal signal conflicts comprise vertical conflicts.
 6. The methodrecited in claim 5, wherein the vertical conflict of a stem of a net ismeasured based on numbers of conflicts due to fault propagationconditions and logic values being forward-implied by the conditions. 7.A method, executed by at least one processor of a computer, comprising:computing internal signal conflict metrics; adding/adjusting test pointsto/at locations selected based on internal signal conflict metrics; andrepeating the computing and the adding/adjusting until one of one ormore predetermined conditions is met.
 8. The method recited in claim 7,wherein the test points are control points.
 9. The method recited inclaim 7, wherein the internal signal conflicts comprise horizontalconflicts.
 10. The method recited in claim 9, wherein the horizontalconflict of a branch of a net in the circuit design is measured based onnumbers of faults being blocked by setting the branch to a signal of “0”and of “1”, respectively.
 11. The method recited in claim 7, wherein theinternal signal conflicts comprise vertical conflicts.
 12. The methodrecited in claim 11, wherein the vertical conflict of a stem of a net ismeasured based on numbers of conflicts due to fault propagationconditions and logic values being forward-implied by the conditions. 13.One or more non-transitory computer-readable media storingcomputer-executable instructions for causing one or more processors toperform a method, the method comprising: determining locations in acircuit design for inserting test points based on internal signalconflicts caused by detecting multiple faults with a single testpattern; inserting test points at the locations.
 14. The one or morenon-transitory computer-readable media recited in claim 13, wherein theinternal signal conflicts comprise horizontal conflicts.
 15. The one ormore non-transitory computer-readable media recited in claim 14, whereinthe horizontal conflict of a branch of a net in the circuit design ismeasured based on numbers of faults being blocked by setting the branchto a signal of “0” and of “1”, respectively.
 16. The one or morenon-transitory computer-readable media recited in claim 13, wherein theinternal signal conflicts comprise vertical conflicts.
 17. The one ormore non-transitory computer-readable media recited in claim 16, whereinthe vertical conflict of a stem of a net is measured based on numbers ofconflicts due to fault propagation conditions and logic values beingforward-implied by the conditions.
 18. The one or more non-transitorycomputer-readable media recited in claim 13, wherein the test points arecontrol points.
 19. One or more non-transitory computer-readable mediastoring computer-executable instructions for causing one or moreprocessors to perform a method, the method comprising: computinginternal signal conflict metrics; adding/adjusting test points to/atlocations selected based on internal signal conflict metrics; andrepeating the computing and the adding/adjusting until one of one ormore predetermined conditions is met.
 20. The one or more non-transitorycomputer-readable media recited in claim 19, wherein the internal signalconflicts comprise horizontal conflicts.
 21. The one or morenon-transitory computer-readable media recited in claim 20, wherein thehorizontal conflict of a branch of a net in the circuit design ismeasured based on numbers of faults being blocked by setting the branchto a signal of “0” and of “1”, respectively.
 22. The one or morenon-transitory computer-readable media recited in claim 19, wherein theinternal signal conflicts comprise vertical conflicts.
 23. The one ormore non-transitory computer-readable media recited in claim 22, whereinthe vertical conflict of a stem of a net is measured based on numbers ofconflicts due to fault propagation conditions and logic values beingforward-implied by the conditions.
 24. The one or more non-transitorycomputer-readable media recited in claim 13, wherein the test points arecontrol points.